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Low Phase Noise, Dual 1-to-6, 3.3V, 2.5V
LVPECL Output Fanout Buffer
8SLVP2106
DATA SHEET
General Description
The 8SLVP2106 is a high-performance differential dual 1:6 LVPECL
fanout buffer. The device is designed for the fanout of high-frequency,
very low additive phase-noise clock and data signals. The
8SLVP2106 is characterized to operate from a 3.3V or 2.5V power
supply. Guaranteed output-to-output and part-to-part skew
characteristics make the 8SLVP2106 ideal for those clock distribution
applications demanding well-defined performance and repeatability.
Two independent buffers with six low skew outputs each are
available. The integrated bias voltage references enable easy
interfacing of single-ended signals to the device inputs. The device is
optimized for low power consumption and low additive phase noise.
Block Diagram
PCLKA
nPCLKA
VCC
VREFA
Voltage
Reference
PCLKB
nPCLKB
VCC
VREFB
Voltage
Reference
QA0
nQA0
QA1
nQA1
QA2
nQA2
QA3
nQA3
QA4
nQA4
QA5
nQA5
QB0
nQB0
QB1
nQB1
QB2
nQB2
QB3
nQB3
QB4
nQB4
QB5
nQB5
Features
• Two 1:6, low skew, low additive jitter LVPECL fanout buffers
• Two differential clock inputs
• Differential PCLKA, nPCLKA and PCLKB, nPCLKB pairs can
accept the following differential input levels: LVDS, LVPECL, CML
• Differential PCLKA, nPCLKA and PCLKB, nPCLKB pairs can also
accept single-ended LVCMOS levels. See Applications section
Wiring the Differential Input Levels to Accept Single-ended Levels
(Figure 1A and Figure 1B).
• Maximum input clock frequency: 2GHz
• Output bank skew: 15ps (typical)
• Propagation delay: 340ps (maximum)
• Low additive phase jitter, RMS: 54fs (maximum)
fREF = 156.25MHz, VPP = 1V, 12kHz - 20MHz: VCC = 3.3V)
• Full 3.3V and 2.5V supply voltage modes
• Maximum device current consumption (IEE): 114mA
• Available in Lead-free (RoHS 6), 40-Lead VFQFN package
• -40°C to 85°C ambient operating temperature
• Supports case temperature 105°C operations
Pin Assignment
30 29 28 27 26 25 24 23 22 21
VCC 31
QB2 32
nQB2 33
QB3 34
nQB3 35
QB4 36
nQB4 37
QB5 38
nQB5 39
VCC 40
8SLVP2106i
40-lead VFQFN
6mm x 6mm x 0.925mm package body
NL Package
Top View
1 2 3 4 5 6 7 8 9 10
20 VCC
19 nQA3
18 QA3
17 nQA2
16 QA2
15 nQA1
14 QA1
13 nQA0
12 QA0
11 VCC
8SLVP2106 REVISION B 6/9/15
1 ©2015 Integrated Device Technology, Inc.
8SLVP2106 DATA SHEET
Pin Descriptions and Characteristics
Table 1. Pin Descriptions
Number
Name
Type
Description
1, 10
nc Unused
Do not connect.
2
3
4
5, 6, 11, 20,
31, 40
7
8
PCLKB
nPCLKB
VREFB
VCC
VREFA
nPCLKA
Input
Input
Output
Power
Output
Input
Pulldown
Pulldown/
Pullup
Non-inverting LVPECL differential clock/data input.
Inverting LVPECL differential clock input.
Bias voltage reference for the PCLKB, nPCLKB input pair.
Pulldown/
Pullup
Power supply pins.
Bias voltage reference for the PCLKA, nPCLKA input pair.
Inverting LVPECL differential clock input.
9
PCLKA
Input
Pulldown Non-inverting LVPECL differential clock/data input.
12, 13
QA0, nQA0
Output
Differential output pair A0. LVPECL interface levels.
14, 15
QA1, nQA1
Output
Differential output pair A1. LVPECL interface levels.
16, 17
QA2, nQA2
Output
Differential output pair A2. LVPECL interface levels.
18, 19
QA3, nQA3
Output
Differential output pair A3. LVPECL interface levels.
21, 30
22, 23
VEE
QA4, nQA4
Power
Output
Negative supply pins.
Differential output pair A4. LVPECL interface levels.
24, 25
QA5, nQA5
Output
Differential output pair A5. LVPECL interface levels.
26, 27
QB0, nQB0
Output
Differential output pair B0. LVPECL interface levels.
28, 29
QB1, nQB1
Output
Differential output pair B1. LVPECL interface levels.
32, 33
QB2, nQB2
Output
Differential output pair B2. LVPECL interface levels.
34, 35
QB3, nQB3
Output
Differential output pair B3. LVPECL interface levels.
36, 37
QB4, nQB4
Output
Differential output pair B4. LVPECL interface levels.
38, 39
QB5, nQB5
Output
Differential output pair B5. LVPECL interface levels.
NOTE: Pulldown and Pullup refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.
Table 2. Pin Characteristics
Symbol
Parameter
CIN
RPULLDOWN
RPULLUP
Input Capacitance
Input Pulldown Resistor
Input Pullup Resistor
Test Conditions
Minimum
Typical
2
51
51
Maximum
Units
pF
k
k
LOW PHASE NOISE, DUAL 1-TO-6, 3.3V, 2.5V LVPECL OUTPUT
FANOUT BUFFER
2
REVISION B 6/9/15
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