8T73S1802 반도체 회로 부품 판매점
1:2 Clock Fanout Buffer and Frequency Divider
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 Integrated Device Technology |
1:2 Clock Fanout Buffer and Frequency Divider 8T73S1802
DATA SHEET
General Description
Features
The 8T73S1802 is a fully integrated clock fanout buffer and frequency
divider. The input signal is frequency-divided and then fanned out to
one differential LVPECL and one LVCMOS output. Each of the
outputs can select its individual divider value from the range of ÷1,
÷2, ÷4 and ÷8. Three control inputs EN, SEL0 and SEL1 (3-level
logic) are available to select the frequency dividers and the output
enable/disable state. The single-ended LVCMOS output is
phase-delayed by 650ps to minimize coupling of LVCMOS switching
into the differential output during its signal transition.
The 8T73S1802 is optimized to deliver very low phase noise clocks.
The VBB output generates a common-mode voltage reference for the
differential clock input so that connecting the VBB pin to an unused
input (nCLK) enables to use of single-ended input signals. The
extended temperature range supports wireless infrastructure,
telecommunication and networking end equipment requirements.
The 8T73S1802 can be used with a 3.3V or a 2.5V power supply. The
device is a member of the high-performance clock family from IDT.
• High-performance fanout buffer clock and fanout buffer
• Input clock signal is distributed to one LVPECL and one LVCMOS
output
• Configurable output dividers for both LVPECL and LVCMOS
outputs
• Supports clock frequencies up to 1000MHz (LVPECL) and up to
200MHz (LVCMOS)
• Flexible differential input supports LVPECL, LVDS and CML
• VBB generator output supports single-ended input signal
applications
• Optimized for low phase noise
• 650ps delay between LVCMOS and LVPECL minimizes coupling
between outputs
• Supply voltage: 3.3V or 2.5V
• -40°C to 85°C ambient operating temperature
• 16 VFQFN package (3mm x 3mm)
8T73S1802 REVISION 1 08/31/15
1 ©2015 Integrated Device Technology, Inc.
8T73S1802 DATA SHEET
Block Diagram
Pin Assignment
CLK
nCLK
VBB
SEL0 Pullup
SEL1 Pullup
EN Pullup
Bias Generator
VCC-1.3V
Control
÷1
÷2
÷4
÷8
QA
nQA
12 11 10
SEL0 13
9
8 VCCO_QB
GND 14
8T73S1802
7 QB
QB SEL1 15 8XXXXXX 6 GND
EN 16
5 GND
12 3 4
16-pin, 3mm x 3mm VFQFN Package
Pin Description and Pin Characteristic Tables
Table 1. Pin Assignment
Pin Number
Name
Type1
Description
1 VCC Power
2 CLK Input
3
nCLK
Input
Power supply voltage for the device core and the inputs.
Non-inverting differential clock input. Compatible with LVPECL, LVDS
and CML signals.
Inverting differential clock input. Compatible with LVPECL, LVDS and
CML signals.
4 VBB Output
5
GND
Power
Bias voltage generator output. Use to bias the nCLK input in
single-ended input applications. VBB = VCC - 1.3V.
Ground supply voltage (GND) and ground return path. Connect to
board GND (0V).
6
GND
Power
Ground supply voltage (GND) and ground return path. Connect to
board GND (0V).
7 QB Output
LVCMOS clock output QB. LVCMOS/LVTTL interface levels.
If this pin is disabled by connecting its power supply pin VCCO_QB to
GND, QB must be left open or connected to GND.
8
VCCO_QB
Power
Positive supply voltage for the QB output. The QB output (if not
connected) can be disabled by connecting this pin to GND.
9
VCCO_QA
Power
10 QA Output
Positive supply voltage for the QA, nQA output. The QA, nQA output (if
not connected) can be disabled by connecting this pin to GND.
Differential clock output QA. LVPECL interface levels.
If this pin is disabled by connecting its power supply pins VCCO_QA to
GND, QA and nQA must be left open or connected to GND.
11
nQA
Output
Differential clock output QA. LVPECL interface levels.
If this pin is disabled by connecting its power supply pins VCCO_QA to
GND, QA and nQA must be left open or connected to GND.
12
VCCO_QA
Power
Positive supply voltage for the QA, nQA output. The QA, nQA output (if
not connected) can be disabled by connecting this pin to GND.
13
SEL0
Input
60k Pullup
Configuration pins. 3-Level interface. See Table 3 for function and Table
4D for interface levels.
1:2 CLOCK FANOUT BUFFER AND FREQUENCY DIVIDER
2
REVISION 1 08/31/15
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제조업체: Integrated Device Technology
( idt )
8T73S1802 buffer
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