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PDF NB3L202K Data sheet ( Hoja de datos )
| Número de pieza | NB3L202K | |
| Descripción | Differential 1:2 HCSL Fanout Buffer | |
| Fabricantes | ON Semiconductor | |
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NB3L202K
2.5 V, 3.3 V Differential 1:2
HCSL Fanout Buffer
Description
The NB3L202K is a differential 1:2 Clock fanout buffer with
High−speed Current Steering Logic (HCSL) outputs. Inputs can
directly accept differential LVPECL, LVDS, and HCSL signals.
Single−ended LVPECL, HCSL, LVCMOS, or LVTTL levels are
accepted with a proper external Vth reference supply per Figures 4
and 6. The input signal will be translated to HCSL and provides two
identical copies operating up to 350 MHz.
The NB3L202K is optimized for ultra−low phase noise, propagation
delay variation and low output–to–output skew, and is DB200H
compliant. As such, system designers can take advantage of the
NB3L202K’s performance to distribute low skew clocks across the
backplane or the motherboard making it ideal for Clock and Data
distribution applications such as PCI Express, FBDIMM, Networking,
Mobile Computing, Gigabit Ethernet, etc.
Output drive current is set by connecting a 475 W resistor from
IREF (Pin 10) to GND per Figure 11. Outputs can also interface to
LVDS receivers when terminated per Figure 12.
Features
• Maximum Input Clock Frequency > 350 MHz
• 2.5 V ±5% / 3.3 V ±10% Supply Voltage Operation
• 2 HCSL Outputs
• DB200H Compliant
• Individual OE Control Pin for Each Output
• 100 ps Max Output−to−Output Skew Performance
• 1 ns Typical Propagation Delay
• 500 ps Typical Rise and Fall Times
• 80 fs Maximum Additive RMS Phase Jitter
• −40°C to +85°C Ambient Operating Temperature
• QFN 16−pin Package, 3 mm x 3 mm
• These Devices are Pb−Free and are RoHS Compliant
Typical Applications
• PCI Express
• FBDIMM
• Mobile Computing
• Networking
• Gigabit Ethernet
www.onsemi.com
MARKING
DIAGRAM
QFN16
1
NB3L
3x3 202K
1
CASE 485AE
ALYWG
G
NB3L202K = Specific Device Code
A = Assembly Location
L = Wafer Lot
Y = Year
W = Work Week
G = Pb−Free Package
(Note: Microdot may be in either location)
ORDERING INFORMATION
See detailed ordering and shipping information page 13 of this
data sheet.
© Semiconductor Components Industries, LLC, 2016
April, 2016 − Rev. 0
1
Publication Order Number:
NB3L202K/D
1 page  
NB3L202K
Table 4. DC CHARACTERISTICS VDD = VDD_O = 3.3 V ±10% or 2.5 V ±5%, TA = −40°C to 85°C
Symbol
Characteristics
Min Typ Max Unit
POWER SUPPLY CURRENT
VDD Core Power Supply Voltage
VDD = 3.3 V ±10%
VDD = 2.5 V ±5%
VDD_O Output Power Supply Voltage
VDD_O = 3.3 V ±10%
VDD_O = 2.5 V ±5%
IDD + IDD_O Total Power Supply Current (all outputs active @ 350 MHz, RREF = 412 W,
RL = 43 W)
Istdby Standby Current, all OE pins de−asserted with inputs @ 350 MHz
lincr Incremental output current for additional output; One OE Enabled
Istdby + lincr Standby Current plus incremental current for one additional differential output;
One OE Enabled @ 350 MHz
2.970
2.375
2.970
2.375
3.3
2.5
3.3
2.5
80
50
15
65
3.630
2.625
3.630
2.625
110
65
23
88
V
V
mA
mA
mA
mA
HCSL OUTPUTS (Notes 4, 5)
VOH
VOL
VOUT
Output HIGH Voltage
Output LOW Voltage
Output Swing (Single−Ended)
Output Swing (Differential)
660
−150
400
800
750
1500
850
mV
mV
mV
DIFFERENTIAL INPUT DRIVEN SINGLE−ENDED (Note 6) (Figures 4 and 6)
VIH CLK_IN/CLK_IN# Single-ended Input HIGH Voltage
VIL CLK_IN/CLK_IN# Single-ended Input LOW Voltage
Vth Input Threshold Reference Voltage Range (Note 7)
VISE Single-ended Input Voltage (VIH − VIL)
DIFFERENTIAL INPUTS DRIVEN DIFFERENTIALLY (Note 8) (Figures 5 and 7)
0.5
GND
0.25
0.5
VDD
VIH − 0.3
VDD − 1.0
VDD
V
V
V
V
VIHD
VILD
Differential Input HIGH Voltage
Differential Input LOW Voltage
0.5 VDD − 0.85 V
0
VIHD −
V
0.25
VID Differential Input Voltage (VIHD − VILD)
VIHCMR Input Common Mode Range (Differential Configuration) (Note 9) (Figure 8)
IIL Input Leakage Current 0 < VIN < VDD (Note 10)
LVTTL / LVCMOS INPUTS (OEx#)
0.25
0.5
−5
1.3
VDD − 0.85
5
V
V
mA
VIH Input HIGH Voltage
2.0
VDD + 0.3
V
VIL Input LOW Voltage
−0.3 0.8 V
IIL Input LOW Current (VIN = GND)
−10 +10 mA
IIH Input HIGH Current (VIN = VDD)
100 mA
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product
performance may not be indicated by the Electrical Characteristics if operated under different conditions.
4. Test configuration is RS = 33.2 W, RL = 49.9, CL = 2 pF, RREF = 475 W.
5. Measurement taken from Single−Ended waveform unless specified otherwise.
6. VIH, VIL, Vth and VISE parameters must be complied with simultaneously.
7. Vth is applied to the complementary input when operating in single−ended mode.
8. VIHD, VILD, VID and VCMR parameters must be complied with simultaneously.
9. The common mode voltage is defined as VIH.
10. Does not include inputs with pulldown resistors.
www.onsemi.com
5
5 Page 
NB3L202K
NB3L202K
Qx
HCSL
Device
Qx
IREF
RREF
Zo = 50 W
100 W
Zo = 50 W
RL = 150 W
100 W
RL = 150 W
LVDS
Device
GND
Figure 12. HCSL Interface Termination to LVDS
MEASUREMENT POINTS FOR DIFFERENTIAL
VOH = 0.525 V
TRise (Clock)
VCross
VOL = 0.175 V
TFall (Clock#)
Figure 13. Single−Ended Measurement Points for Trise, Tfall
Vovs
Vhigh
Vrb
Vrb
Vlow
Vuds
Figure 14. Single−Ended Measurement Points for Vovs, Vuds, Vrb
www.onsemi.com
11
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| Páginas | Total 14 Páginas | |
| PDF Descargar | [ Datasheet NB3L202K.PDF ] | |
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