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PDF YDA147 Data sheet ( Hoja de datos )
| Número de pieza | YDA147 | |
| Descripción | STEREO 5W-15W DIGITAL AUDIO POWER AMPLIFIER | |
| Fabricantes | YAMAHA CORPORATION | |
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YDA147
D- 515
STEREO 5W-15W DIGITAL AUDIO POWER AMPLIFIER
Overview
YDA147 (D-515) is a high-efficiency digital audio power amplifier IC with the maximum output of 15W × 2ch.
YDA147 has a “Pure Pulse Direct Speaker Drive Circuit” that directly drives speakers while reducing distortion of
pulse output signal and reducing noise on the signal, which realizes the highest standard low distortion rate
characteristics and low noise characteristics among digital amplifier ICs in the same class.
In addition, supporting filterless design allows circuit design with fewer external parts to be realized depending on use
conditions.
YDA147 features Power Limit Function, Non-clip Function, and DRC (Dynamic Range Control) Function that were
developed by Yamaha original digital amplifier technology.
YDA147 has overcurrent protection function for speaker output terminals, high temperature protection function, and
lowsupply voltage malfunction prevention function.
Features
Operating supply voltage range
PVDD: 8.0V to 16.5V
Maximum momentary output
20 W×2ch (VDDP=14V, RL=4Ω, THD+N=10%)
15 W×2ch (VDDP=12V, RL=4Ω, THD+N=10%)
Maximum continuous output
15 W*1×2ch
10.5W*1×2ch
(VDDP=15V, RL=8Ω, THD+N=10%, Ta=70°C)
(VDDP=15V, RL=4Ω, THD+N=10%, Ta=25°C)
Distortion Rate (THD+N)
0.01 % (VDDP=12V, RL=8Ω, Po=0.1W, 1kHz)
Residual Noise
48µVrms (VDDP=12V, GAIN[1:0]=L,L, NCDRC[1:0]=L,L)
Efficiency
92 % (VDDP=12V, RL=8Ω)
S/N Ratio
105 dB (VDDP=12V, GAIN[1:0]=L,L, NCDRC[1:0]=L,L)
Channel separation
-80 dB (VDDP=12V, GAIN[1:0]=L,L, NCDRC[1:0]=L,L)
PSRR
60dB (VDDP=12V,Vripple=100mV, 1kHz, GAIN[1:0]=L,L, NCDRC[1:0]=L,L)
Non-clip function/DRC function (switchable)
Power limit function
Clock External Synchronization Function
Master/Slave Synchronization Function using clock outputs
Over-current Protection Function, High Temperature Protection Function,
Low Voltage Malfunction Prevention Function, and DC Detection Function
Sleep Function using SLEEPN terminal and Output Mute Function using MUTEN terminal
Stereo/Monaural Switching Function
Spread Clock Function
Pop Noise Reduction Function
Package
Lead-free 48-pin Plastic SQFP (Exposed stage)
Note) *1: A value based on Yamaha's board implementation conditions (See Note *2 of page 25)
YDA147 CATALOG
CATALOG No.:LSI-4DA147A41
2007.9
1 page  
YDA147
Functional Description
Digital Amplifier Function
YDA147 has digital amplifiers with analog input, PWM pulse output, the maximum output of 20W × 2ch.
Adopting “Pure Pulse Direct Speaker Drive Circuit” reduces distortion and noise on PWM pulse output signal.
Digital Amplifier Gain
The total gain of the digital amplifier varies depending on operation modes, as shown below.
NCDRC1 NCDRC0
LL
LH
HL
HH
GAIN1
L
L
H
H
L
L
H
H
L
L
H
H
L
L
H
H
GAIN0
L
H
L
H
L
H
L
H
L
H
L
H
L
H
L
H
Total Gain
+22dB
+28dB
+34dB
+16dB
+34dB
+40dB
+46dB
+28dB
+34dB
+40dB
+46dB
+28dB
+34dB
+40dB
+46dB
+28dB
Operation Mode
Normal mode
Non-clip: OFF
DRC: OFF
Non-clip mode
DRC1 mode
DRC2 mode
Audio Signal Input
For a differential input, the signal should be input to INLP and INLM terminals (Lch) and to INRP and INRM terminals
(Rch) through a DC-cut capacitor (CIN).
On the contrary, for a single-ended input, the signal should be input to INLP terminal (Lch) and to INRP terminal (Rch)
through a DC-cut capacitor (CIN). At this time, INLM and INRM terminals should be connected to AVSS through DC-cut
capacitors (CIN) with the same value.
In the differential input mode, use signal sources with the same impedance to reduce pop-noise. Its value should be 10kΩ or
less. Use a DC-cut capacitor (CIN) of 1µF. (The capacitance value should be less than 1.5µF throughout the operating
temperature range.)
(Cautions)
When inputting audio signals in Power-off state ( PVDD < VHUVLL ) or Sleep state, current may flow toward the former
device from YDA147's ground, through each protection circuit of analog pins (INLP, INLM, INRP, and INRM).
For this reason, audio signals should not be input in Power-off state ( PVDD < VHUVLL ) or Sleep state.
5
5 Page 
YDA147
Sleep Function
YDA147 shifts into sleep mode when SLEEPN terminal goes to “L” level.
In the sleep mode, all functions stop and consumption current is minimized ( SLEEP).
When shifting into sleep mode during any protection mode, the protection mode is cancelled and PROTN terminal output
becomes Hi-Z state.
The digital amplifier output becomes Weak Low (a state grounded through a high resistance).
AVDD and VREF outputs are pulled down.
When the level at SLEEPN terminal is changed from “L” to “H” under the condition that the voltage at PVDDREG
terminal is higher than the threshold voltage (VHUVLH) for low voltage malfunction prevention cancellation, the sleep
mode is cancelled and the state shifts into the normal operation state after the period of sleep recovery time (tWU).
Mute Function
YDA147 shifts into mute mode when MUTEN terminal goes to “L” level.
In the mute mode, the digital amplifier output becomes Weak Low (a state grounded through a high resistance).
When the level at MUTEN terminal is changed from “L” to “H” under the condition that the voltage at PVDDREG
terminal is higher than the threshold voltage (VHUVLH) for low voltage malfunction prevention cancellation and state of
SLEEPN terminal=H, the mute mode is cancelled and the state shifts into the normal operation state after the period of
mute recovery time (tMRCV).
Clock Control Function
The setting of CKIN terminal controls the clock mode as shown below.
CKIN terminal Setting
L fixed
H fixed
Mode
Internal Clock mode
Internal Clock (Spread clock) mode
Clock input
External Clock mode
CKOUT
Internal Clock (frequency: fCK) output
Internal Clock (Spread Clock) frequency: (fCK)
output
CKIN input buffer output (frequency: fCKIN)
When CKIN terminal is held L or H level, internal clock mode is selected to generate a clock internally.
And, when CKIN terminal is held H level, Spread Clock function operates to reduce EMI.
When an external clock is input to CKIN terminal, its frequency should be fCKIN.
Do not use with CKIN terminal left open.
Stereo/Monaural Switching Function
When INRP and INRM terminals (Rch input) are connected to AVDD, monaural mode is selected.
In the monaural mode, input signals input to INLP and INLM terminals (Lch input) are output from Lch and Rch digital
amplifiers.
With the monaural mode, parallel operation can be realized by connecting OUTPL to OUTPR and connecting OUTML
to OUTMR.
For details of connections, see “Single operation in monaural mode” (See page 20) in the “Examples of Application
Circuits.”
The switching between stereo and monaural modes should be performed under the following conditions.
Before PVDD power-on (lower than the PVDD shut-down threshold voltage)
Digital Amplifier Pop Noise Reduction Function
Pop noise that may occur at the power-on, power-off, power-down, and power-down cancel operations, etc. is reduced by
minimizing an output offset voltage.
Multi-chip Synchronization Function
The external clock synchronization function and clock output function are prepared and the use of master/slave
configuration realizes carrier clock synchronization.
When using it with multi chips synchronized, one is used as a master chip and the other is used as a slave chip. At this
time, connect CKOUT terminal of a master chip to CKIN terminal of a slave chip.
When using 3 chips (master/slave1/slave2), connect CKOUT terminal of a slave1 chip to CKIN terminal of a slave2 chip.
For details of connections, see “MASTER-SLAVE operation” (See page 23 and 24) in the “Examples of Application
Circuits.”
PVDD pins should be connected each other on a board.
11
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet YDA147.PDF ] | |
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