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AJAV-5601 반도체 회로 부품 판매점

Power Amplifier



AVAGO 로고
AVAGO
AJAV-5601 데이터시트, 핀배열, 회로
AJAV-5601
W-CDMA/HSPA Band I Power Amplifier
Data Sheet
Description
The AJAV-5601 is a complete, high-performance power
amplifier for W-CDMA and HSPA wireless communica-
tions. Based on a unique, patented architecture, the AJAV-
5601 integrates circuitry for TX filtering, RF coupling,
power regulation, input and output matching and power
control. The PA is powered by a single connection to the
battery and is implemented in a standard CMOS process.
Pin Assignments
Top View (x-ray)
VBAT
RFI
VM1
VM0
VEN
GND
PAD
VBAT
RFO
CPLI
GND
CPLO
US Patent # 7,728,661; 7,768,350;
7,872,528; 8,022,766
Other patents pending
Functional Block Diagram
Features
High-performance 3G power amplifier
- UMTS Band I (1920 – 1980 MHz)
- W-CDMA, HSPA, and HSPA+ Compliant
Integrated TX filtering
- Delivers best noise in the industry
Integrated directional coupler
Integrated regulators and PA bias
Single direct connection to the battery
- No external switches or isolation inductors
High linear efficiency
Low average current
High capacity CMOS process
Small 3×3 mm package
Applications
Smartphones, data cards and 3G modules
Tablets, netbooks and network PCs
E-books and wireless electronic readers
Top View
VBAT
AJAV-5601
REGULATOR / BIAS
RFI
INPUT
MATCH
PA
CONTROL
VM0 VM1 VEN
OUTPUT
MATCH
RFO
CPLI
CPLO
Free Datasheet http://www.datasheet4u.com/


AJAV-5601 데이터시트, 핀배열, 회로
Electrical Characteristics
Table 1. Absolute Minimum and Maximum Ratings [1]
Parameter
Symbol
Condition
Min Typ Max Unit
Supply Voltage [2]
Control Voltage [3]
RF Input Power [4]
VBATT
VCTRL
VCTRL < VBATT
-0.3 -
-0.3 -
--
4.5 V
4.5 V
+10 dBm
Electrostatic Discharge (ESD) [5]
Human Body Model (HBM)
-
- 3.0 kV
Storage Temperature
TSTG
-55 -
125 °C
Notes:
1. Permanent device damage may occur if the ratings above are exceeded. Functional operation is not guaranteed under these conditions and
should be restricted to the recommended operating conditions in Table 2. Exposure to absolute ratings for extended periods may affect device
reliability.
2. Supply voltage is applied to VBAT pin.
3. Control voltages are applied to VEN, VM0, VM1 pins.
4. RF input is applied to RFI, CPLI pins.
5. For all pins.
Table 2. Operating Conditions [1]
Parameter
Symbol
Condition
Min Typ Max
Supply Voltage [2]
Control Voltage – High [3]
Control Voltage – Low [3]
VBATT
VIH
VIL
VIH < VBATT
2.5 3.8 4.2
1.3 1.8 VBATT
0.0 -
0.5
Ambient Temperature
TA
-30 25
90
Notes:
1. To ensure proper operation, the VEN pin should be asserted from VIL to VIH at least 2 ms after power is applied to the VBAT pin.
2. Device remains functional down to VBATT = 2.5 V. At VBATT < 3.4 V, output power is derated by 0.5 dB.
3. Logic states for VEN, VM0, VM1 pins.
Unit
V
V
V
°C
Table 3. Mode Control Logic [1]
Mode
Output Power Range [2]
VEN VM0 VM1
High Power Mode (HP)
16.5 dBm < POUT ≤ PMAX
High Low Low
Mid Power Mode (MP)
6.0 dBm < POUT ≤ 16.5 dBm
High
High
Low
Low Power Mode (LP)
POUT ≤ 6.0 dBm
High
High
High
Powerdown
Low X
X
Notes:
1. The VM0 and VM1 pins are controlled externally to achieve maximum PA efficiency. High and low logic states are specified in Table 2.
2. Maximum linear output power, PMAX, is defined in Table 4.
2
Free Datasheet http://www.datasheet4u.com/




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