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SMP04EQ 반도체 회로 부품 판매점

CMOS Quad Sample-and-Hold Amplifier



Analog Devices 로고
Analog Devices
SMP04EQ 데이터시트, 핀배열, 회로
a
FEATURES
Four Independent Sample-and-Holds
Internal Hold Capacitors
High Accuracy: 12 Bit
Very Low Droop Rate: 2 mV/s typ
Output Buffers Stable for CL 500 pF
TTL/CMOS Compatible Logic Inputs
Single or Dual Supply Applications
Monolithic Low Power CMOS Design
APPLICATIONS
Signal Processing Systems
Multichannel Data Acquisition Systems
Automatic Test Equipment
Medical and Analytical Instrumentation
Event Analysis
DAC Deglitching
CMOS Quad
Sample-and-Hold Amplifier
SMP04*
FUNCTIONAL BLOCK DIAGRAM
VDD
SMP04
VIN1
S/H1
VIN2
S/H2
VIN3
S/H3
VIN4
S/H4
VSS
VSS
VSS
VSS
VOUT1
VOUT2
VOUT3
VOUT4
DGND
VSS
GENERAL DESCRIPTION
The SMP04 is a monolithic quad sample-and-hold; it has four
internal precision buffer amplifiers and internal hold capacitors.
It is manufactured in ADI’s advanced oxide isolated CMOS
technology to obtain the high accuracy, low droop rate and fast
acquisition time required by data acquisition and signal process-
ing systems. The device can acquire an 8-bit input signal to
± 1/2 LSB in less than four microseconds. The SMP04 can
operate from single or dual power supplies with TTL/CMOS
logic compatibility. Its output swing includes the negative supply.
The SMP04 is ideally suited for a wide variety of sample-and-
hold applications, including amplifier offset or VCA gain adjust-
ments. One or more can be used with single or multiple DACs
to provide multiple setpoints within a system.
The SMP04 offers significant cost and size reduction over
equivalent module or discrete designs. It is available in a
16-lead hermetic or plastic DIP and surface mount SOIC
packages. It is specified over the extended industrial tem-
perature range of –40°C to +85°C.
*Protected by U.S. Patent No. 4,739,281.
REV. D
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700
World Wide Web Site: http://www.analog.com
Fax: 781/326-8703
© Analog Devices, Inc., 1998


SMP04EQ 데이터시트, 핀배열, 회로
SMP04–SPECIFICATIONS
ELECTRICAL CHARACTERISTICS (@ VDD = +12.0 V, VSS = DGND = 0 V, RL = No Load, TA = Operating Temperature Range
specified in Absolute Maximum Ratings, unless otherwise noted.)
Parameter
Linearity Error
Buffer Offset Voltage
Hold Step
Droop Rate
Output Source Current1
Output Sink Current1
Output Voltage Range
LOGIC CHARACTERISTICS
Logic Input High Voltage
Logic Input Low Voltage
Logic Input Current
DYNAMIC PERFORMANCE2
Acquisition Time3
Acquisition Time3
Hold Mode Settling Time
Slew Rate4
Capacitive Load Stability
Analog Crosstalk
SUPPLY CHARACTERISTICS
Power Supply Rejection Ratio
Supply Current
Power Dissipation
Symbol
VOS
VHS
V/t
ISOURCE
ISINK
OVR
VINH
VINL
IIN
tAQ
tAQ
tH
SR
CL
PSRR
IDD
PDIS
Conditions
VIN = 6 V
VIN = 6 V, TA = +25°C to +85°C
VIN = 6 V, TA = –40°C
VIN = 6 V, TA = +25°C
VIN = 6 V
VIN = 6 V
RL = 20 k
RL = 10 k
TA = +25°C, 0 V to 10 V Step to 0.1%
–40°C TA +85°C
TA = +25°C, 0 V to 10 V Step to 0.01%
To 1 mV
RL = 20 k
<30% Overshoot
0 V to 10 V Step
10.8 V VDD 13.2 V
Min Typ
0.01
–10 ± 2.5
2.5
2
1.2
0.5
0.06
0.06
2.4
0.5
3.5
3.75
9
1
34
500
–80
60 75
4
Max
+10
4
5
25
10.0
9.5
0.8
1
4.25
5.25
7
84
Units
%
mV
mV
mV
mV/s
mA
mA
V
V
V
V
µA
µs
µs
µs
µs
V/µs
pF
dB
dB
mA
mW
ELECTRICAL CHARACTERISTICS (@ VDD = +5.0 V, VSS = –5.0 V, DGND = 0.0 V, RL = No Load, TA = Operating Temperature
Range specified in Absolute Maximum Ratings, unless otherwise noted.)
Parameter
Symbol Conditions
Min
Linearity Error
Buffer Offset Voltage
Hold Step
Droop Rate
Output Resistance
Output Source Current1
Output Sink Current1
Output Voltage Range
LOGIC CHARACTERISTICS
Logic Input High Voltage
Logic Input Low Voltage
Logic Input Current
DYNAMIC PERFORMANCE2
Acquisition Time3
Acquisition Time3
Hold Mode Settling Time
Slew Rate5
Capacitive Load Stability
SUPPLY CHARACTERISTICS
Power Supply Rejection Ratio
Supply Current
Power Dissipation
VOS
VHS
V/t
ROUT
ISOURCE
ISINK
OVR
VINH
VINL
IIN
tAQ
tAQ
tH
SR
CL
PSRR
IDD
PDIS
VIN = 0 V
VIN = 0 V, TA = +25°C to +85°C
VIN = 0 V, TA = –40°C
VIN = 0 V, TA = +25°C
VIN = 0 V
VIN = 0 V
RL = 20 k
–3 V to +3 V Step to 0.1%
–3 V to +3 V Step to 0.01%
To 1 mV
RL = 20 k
<30% Overshoot
± 5 V VDD ≤ ± 6 V
–10
1.2
0.5
–3.0
2.4
500
60
NOTES
1Outputs are capable of sinking and sourcing over 20 mA, but linearity and offset are guaranteed at specified load levels.
2All input control signals are specified with tR = tF = 5 ns (10% to 90% of +5 V) and timed from a voltage level of 1.6 V.
3This parameter is guaranteed without test.
4Slew rate is measured in the sample mode with a 0 V to 10 V step from 20% to 80%.
5Slew rate is measured in the sample mode with a –3 V to +3 V step from 20% to 80%.
Specifications are subject to change without notice.
–2–
Typ
0.01
± 2.5
2.5
2
1
0.5
3.6
9
1
3
75
3.5
Max
+10
4
5
25
+3.0
0.8
1
11
5.5
55
Units
%
mV
mV
mV
mV/s
mA
mA
V
V
V
µA
µs
µs
µs
V/µs
pF
dB
mA
mW
REV. D




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